This invention relates to monolithic amplifiers having the combination of low noise, low input bias current, and high speed.
The need exists for monolithic operational amplifiers with performance more nearly approaching that of an "ideal" operational amplifier having low noise, low input bias current, and high speed operation. FET (field effect transistor) input devices can provide the needed low bias current, but FETs fabricated using conventional monolithic IC manufacturing processes have relatively low bandwidth. Using prior circuit topologies, it has been possible to construct FET input amplifiers with either low noise or high speed, but not the combination of both. When an input FET is used as a gain stage it is capable of low noise operation, but its speed of operation is greatly limited. When an input FET is used as a voltage follower "in front of" a bipolar transistor gain stage, it is capable of higher speed operation, but also has higher noise. The circuit of the present invention provides a combination of the best low noise and high speed features of both of the prior kinds of FET input amplifiers.
FIG. 1 shows a common prior art amplifier designed to minimize noise and maximize signal-to-noise ratio. In the circuit of FIG. 1, the width-to-length geometry ratio of the P channel input JFETS 1 and 2 is large, typically approximately 80. The current I produced by current source 20 typically is about 400 microamperes.
As known to those skilled in the art, increasing the Gm of a JFET (Junction Field Effect Transistor) results in improved noise performance. For a particular manufacturing process and JFET channel length, there are two ways to increase Gm. One is to increase the channel width of the JFET. The other way is to increase the drain-source current. It is often impractical to increase the drain-source current to increase Gm. The theoretical voltage noise produced in JFETs is proportional to 1/SQRT(Gm). Therefore, low noise operation is achieved by making Gm large. Increasing Gm also has the effect of reducing the contribution of other noise sources. For example, if operational amplifier 3 has differential noise on its inputs, the noise imparts a signal noise voltage across resistors 4 and 5, and hence causes signal noise currents to flow through JFETs 1 and 2. As the Gm of the JFETs 1 and 2 increase, the amount of noise signal that has to be compensated by .DELTA.V.sub.IN decreases. (.DELTA.V.sub.IN is equal to V.sub.IN.sup.+ -V.sub.IN .sup.-.) Therefore, the effect of such noise sources is reduced by increasing Gm.
The large transconductance Gm obtained by use of large JFET channel widths results in low noise levels, but also results in slow speed, because the large channel widths result in large gate-to-drain capacitances C.sub.GD between input conductors 16 and 17 and drain conductors 18 and 19, respectively. As a result of "Miller Multiplication", the capacitances C.sub.GD are multiplied by the gains of the two "halves" of the differential amplifier, respectively.
As a result of the large C.sub.GD capacitance of the low noise JFET and Miller multiplication of that C.sub.GD capacitance, the circuit of FIG. 1 is unsuitable for use in applications requiring high bandwidth. The large C.sub.GD introduces phase shifts that necessitate use of larger compensation capacitors, which in turn decrease slew rate.
FIG. 2 shows another typical prior art operational amplifier which is designed for high speed. However, this circuit is characterized by a low signal-to-noise ratio. The performance-degrading effect of the of the Miller feedback capacitance C.sub.GD of FIG. 1 is avoided in the circuit of FIG. 2 by using source followers 1,22, and 2,23 instead of the inverting stages 1,4 and 2,5 of FIG. 1 because the source followers 1,22 and 2,23 drive a pair of emitter-coupled PNP bipolar transistors 6 and 7 with very low parasitic base-collector capacitances. The circuit of FIG. 2 therefore can have high bandwidth and fast settling, but it suffers from high noise.
The high noise is caused by the addition of noise in resistors 6A and 7A and transistors 6 and 7 to noise in input JFETs 1 and 2. This noise is in addition to noises present in the circuit of FIG. 1. The circuit of FIG. 2 also has high power dissipation due to use of the three current sources 22, 23, and 24.
Use of emitter degeneration resistors 6A and 7A in series with emitters of transistors 6 and 7 is necessary to reduce the gain of the circuit and the size of the compensation capacitor necessary to achieve high speed operation. Such degeneration resistors add a resistive thermal noise to the voltage noise level referred back to the inputs 16 and 17.
Up to now, no one has been able to provide a monolithic integrated circuit operational amplifier or the like having both high speed performance, low noise performance, and very low input bias currents. There remains an unmet need for such an amplifier.